1. Field of the Invention
The present invention related to a semiconductor integrated circuit device and in particular to a semiconductor integrated circuit device provided therein with a plurality of internal power source voltage generating circuits.
2. Related Art
In recent years, a semiconductor memory has a plurality of internal power source voltage generating circuits mounted on a semiconductor chip. When all the internal power source voltage generating circuits mounted are simultaneously actuated at a time of power supply to the chip, peak current of about several hundreds mA is generated. In order to prevent such large current from being generated, an approach where generation of such peak current is suppressed by activating the internal power source voltage generating circuits individually or by grouping these circuits into small members to activate them for each group at a time of power supply has been employed.
In order to activate a plurality of internal power source voltage generating circuits individually or divide these circuits into small groups to activate them for each group, a control circuit which actuates respective internal power source voltage generating circuits in a predetermined actuation order must be provided. The control circuit requires an output signal of a level determining circuit which determines whether or not output voltages of individual internal power source voltage generating circuits have reached an expected value, (makes determination about acceptance or rejection of a set completion) and it is constituted so as to activate, when the determination is affirmative (namely when each internal power source voltage generating circuit has reached the expected value), the next internal power source voltage generating circuit.
For example, a configuration of a conventional semiconductor integrated circuit device having a plurality of internal power source voltage generating circuits is shown in FIG. 8. The conventional semiconductor integrated circuit device is a semiconductor memory, and is provided with a plurality of internal power source voltage generating circuits, namely, a VPP generating circuit 5, a VBLH generating circuit 6, and a VBB generating circuit 8. The internal power source voltage generating circuits are inputted with a reference voltage VREF generated from a VREF generating circuit 2, power source voltages VCC and VSS (not shown) inputted externally of a semiconductor chip.
A voltage VPP generated from the VPP generating circuit 5 is used for driving a word line, a voltage VBLH generated from the VBLH generating circuit 6 is a potential indicating “H” level of a bit line, and a voltage VBB generated from the VBB generating circuit 8 is used as a substrate voltage.
The VREF generating circuit 2 generates a reference voltage VREF when power source voltages VCC and VSS are applied to the semiconductor chip. A VCCON signal generating circuit 10 outputs a signal VCCON which reaches “H” level when the power source voltages VCC and VSS are applied to the semiconductor chip and the power source voltage VCC reaches a predetermined level (for example, 1.5V). A VREF timer 12 operates based upon the signal VCCON, and outputs a signal VPPGO which changes to “H” level when a level of the reference voltage VREF becomes stable.
As shown in FIG. 9, the VPP generating circuit 5 is provided with a voltage boosting circuit 5a and a level determining circuit 5b. The voltage boosting circuit 5a performs a voltage boosting action based upon the signal VPPGO and an output signal VPPLIMIT of the level determining circuit 5b to generate a voltage VPP. The level determining circuit 5b operates based upon the reference voltage VREF and the output voltage VPP of the voltage boosting circuit 5a and generates a control signal VPPLIMIT that changes to “H” level when the voltage VPP reaches an expected value.
A specific configuration of the level determining circuit 5b is shown in FIG. 10. The level determining circuit 5b is provided with resistors 61 and 62 connected serially, capacitors 63 and 65, a current mirror circuit 64, and inverters 66 and 67. The resistor 61 receives a voltage VPP at one end thereof, and the other end thereof is connected to one end of the resistor 62. The other end of the resistor 62 is connected to a power source VSS. Such design is employed that a ratio of a resistance value of the resistor 61 to that of the resistor 62 is 22:13, for example. This is for setting a potential VPPVREF at a connection point of the resistor 61 and the resistor 62, namely, a divided voltage to 1.3V, when the voltage VPP is 3.5V.
The current mirror circuit 64 is constituted of P-channel transistors P1 and P2, and N-channel transistors N1, N2, and N3. The gate of the transistor N1 is applied with a divided voltage VPPVREF and the gate of the transistor N2 is applied with a reference voltage VREF. The gate of the transistor N1 is connected with the capacitor 63, and the gate of the transistor N2 is connected with the capacitor 65. The capacitors 63 and 65 are provided for suppressing vibrations of levels of the divided voltage VPPVREF and the reference voltage VREF.
The inverters 66 and 67 are connected in series, and they receive a voltage of a connection node of the transistor P2 and the transistor N2 in the current mirror circuit 64 so that the inverter 67 outputs a control signal VPPLIMIT. When the voltage VPP exceeds 3.5V, VPPVREF>VREF, the control signal VPPLIMIT changes from “L” level to “H” level. When the control signal VPPLIMIT changes to “H” level, the voltage boosting circuit 5a stops its voltage boosting action.
Thus, when the control signal VPPLIMIT generated from the VPP generating circuit 5 becomes “H” level, because the VPPGO signal is also in “H” level, a control circuit 14 operates to feed a control signal VBLHGO whose level has changed to “H” level to the VBLH generating circuit 6 and the control circuit 16, as shown in FIG. 8. A specific configuration of the control circuit 14 is shown in FIG. 11. The specific control circuit 14 is provided with an inverter 71, cross-connected NAND circuits 72 and 73, and an inverter 74. The control signal VPPGO is inputted into the NAND circuit 72, and the control signal VPPLIMIT is inputted into the NAND circuit 73 via the inverter 71. An output of the NAND circuit 72 serves as the control signal VBLHGO via the inverter 74. An operation of the control circuit 14 is shown in FIG. 12. As understood from the above explanation and the description in FIG. 12, the control signal VPPGO first becomes “H” level. Thereafter, when the control signal VPPLIMIT becomes “H” level, the control circuit 14 operates so that the control signal VBLHGO becomes “H” level.
When the control signal VBLHGO whose level has changed to “H” is inputted, as shown in FIG. 8, the VBLH generating circuit 6 operates to generate a voltage VBLH, and when the voltage VBLH reaches an expected value, a control signal VBLHLIMIT generated from the VBLH generating circuit changes to “H” level. As a result, the control circuit 16 operates to change the level of the control signal VBBGO from “L” to “H”. The control signal VBBGO changed to “H” level is feed out to the VBB generating circuit 8 and a control circuit 18. The VBB generating circuit 8 operates based upon the control signal VBBGO changed to “H” level to generate a voltage VBB. When the voltage VBB reaches an expected value, the control signal VBBLIMIT fed from the VBB generating circuit 8 to the control circuit 18 changed to “H” level and the control circuit 18 operates to output a control signal CHRDY showing completion of preparation of the semiconductor chip.
Waveforms of various voltages at a time of power application to the semiconductor memory shown in FIG. 8 are shown in FIG. 13. When power is applied to the semiconductor memory, first, the voltage VCC rises and the reference voltage VREF also increases. When the voltage VCC reaches a predetermined level, a VCCON signal also rises rapidly and the levels of the voltage VCC and the VCCON signal become constant levels (for example, 2.5V). Thereafter, a VPPGO signal rises so that a voltage VPP is produced to rise rapidly. Thereafter, a voltage VBLH is produced to rise rapidly. After the voltage VBLH rises, a voltage VBB is produced to reach a predetermined value. As a result, the control signal CHRDY changes to “H” level. In FIG. 13, after the VPPGO, VCC, VCCON, and CHRDY rise, they become constant values (for example, VCC=2.5V).
Thus, the internal power source voltage generating circuits of the conventional semiconductor integrated circuit device are constituted in a circuit of a self-matching type to compare the reference potential VREF always produced in the chip and each internal power source voltage level (an expected value) with each other to perform a level adjustment automatically. Therefore, various internal power source voltage values expected during an ordinary operation after source supplying are set in the level determining circuit. Conventionally, the control circuit at a time of power supplying is operated based upon an output of the level determining circuit.
Though a low voltage in power source voltage VCC for a semiconductor memory advances, set values for internal power source voltages are not so decreased. Particularly, it is difficult for the power source VPP for driving word lines produced in the voltage boosting circuit to operate at an allowable minimum value VCCmin of the power source voltage due to a structure of the circuit. For example, when a product with a power source VPP of 3.5V is fabricated with a product with a power source voltage VCC of 2.5V, a voltage boosting circuit with a one-stage constitution is used, but the voltage boosting circuit can not produce a voltage exceeding a voltage of VCC (2.5V)×2 theoretically. In fact, an operation guaranteed range for a device is defined in addition to a guaranteed range for an operation speed. In view of such a fact, it is necessary to produce VPP=3.5 V near VCC=2.1 V. Such a value will not cause any problem to a circuit operation theoretically.
However, when the power source voltage VCC is the allowable minimum value VCCmin, such a case occurs that a voltage VPP at a time of power application can not exceed a circuit threshold of the level determining circuit 5b. This means that a reference voltage VREF produced in a chip becomes higher than a design expected value due to a manufacturing process. As understood from FIG. 10, when the reference voltage VREF becomes high like this case, since a circuit threshold of the level determining circuit 5b increases, the voltage boosting circuit 5a must output a voltage VPP with a higher level. In this case, the voltage boosting circuit may be required to operate to output a voltage exceeding an operation limit value at the allowable minimum value VCCmin, namely, a limit value of a voltage produced based upon the allowable minimum value VCCmin. When the voltage boosting circuit is required for an operation for outputting a voltage exceeding the operation limit value at the allowable minimum value VCCmin, the control signal VPPLIMIT does not change to “H” level for all time, and the control circuit 14 does not proceed to a normal operation. Accordingly, the semiconductor chip is put in a non-normal operation at a time of power application.
Such a fact is unavoidable that the level of the reference voltage VREF fluctuates due to a manufacturing process, and a problem about the fluctuation is solved by adjusting the level of the allowable minimum value VCCmin using a fuse circuit or the like. However, in the semiconductor memory, the level adjustment using a fuse circuit is performed when a memory cell is replaced with a redundant cell. Therefore, when the level of the reference voltage VREF fluctuates due to a manufacturing process, a level evaluation to the allowable minimum value VCCmin is once stopped, and determination about good/bad of the memory cell is made. Then, after the level of the VCCmin is adjusted using a fuse circuit or the like, the level evaluation to the VCCmin is performed again. Therefore, there is a problem that the number of evaluation steps increases, which results in increase in evaluation time and rise in manufacturing cost.